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USBDFXXW5
EMI filter and line termination for USB downstream ports
Applications
EMI Filter and line termination for USB downstream ports on:

Desktop computer Notebooks Workstations USB Hubs
SOT323-5L
Functional diagram
Rt
Features
D+ In
D+ Out
Ct Rd

Monolithic device with recommended line termination for USB downstream ports Integrated Rt series termination and Ct bypassing capacitors. Integrated ESD protection Small package size
D- In Gnd
Ct
Rd
D- Out
Rt
Description
The USB specification requires USB downstream ports to be terminated with pull-down resistors from the D+ and D- lines to ground. On the implementation of USB systems, the radiated and conducted EMI should be kept within the required levels as stated by the FCC regulations. In addition to the requirements of termination and EMC compatibility, the computing devices are required to be tested for ESD susceptibility. The USBDFXXW5 provides the recommended line termination while implementing a low pass filter to limit EMI levels and providing ESD protection which exceeds IEC 61000-4-2 level 4 standard. The device is packaged in a SOT323-5L, which is a very small (50% smaller than the standard SOT23).
USBDF01W5 USBDF02W5 Tolerance
Rt 33 15 10%
Rd 15 k 15 k 10%
Ct 47 pF 47 pF 20%
Order codes
Part number USBDF01W5 USBDF02W5 Marking UD1 UD2
Benefits

EMI / RFI noise suppression Required line termination for USB downstream ports ESD protection exceeding IEC61000-4-2 level 4 IPADTM technology provides high flexibility in the design of high density boards Tailored to meet USB 1.1 standard
Complies with the following standards
IEC 61000-4-2, level 4 15 kV (air discharge) 8 kV (contact discharge) MIL STD 883C, Method 3015-6 Class 3 C = 100 pF R = 1500 W 3 positive strikes and 3 negative strikes (F = 1 Hz)
TM: IPAD is a trademark of STMicroelectronics
September 2006
Rev 3
1/11
www.st.com 11
Characteristics
USBDFXXW5
1
Characteristics
Table 1.
Symbol VPP Tj Tstg TL Pr
Absolute maximum ratings (Tamb = 25 C)
Parameter ESD discharge IEC 61000-4-2, contact discharge ESD discharge - MIL STD 883 - Method 3015-6 Operating junction temperature range Storage temperature range Lead solder temperature (10 second duration) Power rating per resistor Value 15 25 -40 to 150 - 55 to +150 260 100 Unit kV C C C mW
Table 2.
Symbol VBR VF
Electrical characteristics (Tamb = 25 C)
Parameters Diode breakdown voltage Diode forward voltage drop Test conditions IR = 1 mA IF = 50 mA Min 6 0.9 Typ Max Unit V V
2
Application information
Figure 1. USB Standard requirements
+Vbus 1.5k
Rt
D+
Twisted pair shielded
D+
Rt Ct Rt
Full-speed or Low-speed USB Transceiver
Ct Rt
Full-speed USB Transceiver
DHost or Hub port
Ct 15k 15k
Zo = 90ohms 5m max
DCt
Hub 0 or Full-speed function
FULL SPEED CONNECTION
+Vbus 1.5k
Rt
D+
Untwisted unshielded
D+
Rt Ct Rt
Full-speed or Low-speed USB Transceiver
Ct Rt
Low-speed USB Transceiver
DHost or Hub port
Ct 15k 15k
3m max
DCt
Hub 0 or Low-speed function
LOW SPEED CONNECTION
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USBDFXXW5 Figure 2. Application example
Downstream port Upstream port
D+ (1) D- (2)
+Vbus
Application information
D+
CABLE
USBDF xxW5
DD- (1) D+ (2)
USBUF xxW6
Host/Hub USB port transceiver
Peripheral transceiver
(1) for a low-speed port (2) for a full-speed port
2.1
EMI filtering
Current FCC regulations requires that class B computing devices meet specified maximum levels for both radiated and conducted EMI.

Radiated EMI covers the frequency range from 30 MHz to 1 GHz. Conducted EMI covers the 450 kHz to 30 MHz range.
For the types of devices utilizing the USB the most difficult test to pass is usually the radiated EMI test. For this reason the USBDF device aims to minimize radiated EMI. The differential signal (D+ and D-) of the USB does not contribute significantly to radiated or conducted EMI because the magnetic field of the two conductors exactly cancels each other. The inside of the PC environment is very noisy and designers must minimise noise coupling from the different sources. D+ and D- must not be routed near high speed lines (clocks...). Induced common mode noise can be minimised by running pairs of USB signals parallel to each other and running grounded guard trace on each side of the signal pair from the USB controller to the USBDF device. If possible, locate the USBDF device physically near the USB connectors. Distance between the USB controller and the USB connector must be minimized. The 47 pF (Ct) capacitors are used to divert high frequency energy to ground and for edge control, and must be placed between the USB Controller and the series termination resistors (Rt). Both Ct and Rt should be placed as close to the mSB Controller as practicable. The USBDFXXW5 ensure a filtering protection against electroMagnetic and radio-frequency Interference thanks to its low-pass filter structure. This filter is characterized by the following parameters :

cut-off frequency Insertion loss high frequency rejection
Figure 4. shows the attenuation curve for frequencies up to 3 GHz.
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Application information
USBDFXXW5
Figure 3.
Measurement configuration
Figure 4.
USBDFXXW5 attenuation curve
Insertion loss (dB) 0
TEST BOARD
50 TG OUT
RF IN
-10
50
UD1
Vg
-20
-30 1 10 100 F (MHz) 1000 3000
2.2
ESD protection
In addition to the requirements of termination and EMC compatibility, computing devices are required to be tested for ESD susceptibility. This test is described in the IEC 61000-4-2 and is already in place in Europe. This test requires that a device tolerates ESD events and remain operational without user intervention. The USBDFXXW5 is particularly optimized to perform ESD protection. ESD protection is based on the use of device which clamps at :
VINPUT = VBR + Rd.Ipp
This protection function is split in 2 stages. As shown in Figure 5., the ESD strikes are clamped by the first stage S1 and then the remaining overvoltage is applied to the second stage through the resistor R. Such a configuration makes the output voltage very low at the Vout level. Figure 5. USBDFXXW5 ESD clamping behavior
Rg
S1
R
S2
Rd
VPP
Vinput Voutput
Rd
Rload
VBR
VBR
Device to be protected
ESD Surge
USBDFXXW5
4/11
USBDFXXW5
Application information
To have a good approximation of the remaining voltages at both Vin and Vout stages, we give the typical dynamical resistance value Rd. Taking into account the following hypothesis: Rt > Rd, Rg > R and Rload > Rd, gives these formulas::
Vinput = Rg.VBR + Rd. Vg Rg Rt.VBR + Rd. Vinput Rt
Voutput =
The results of the calculation done for VPP = 8 kV, Rg = 330 W (IEC61000-4-2 standard), VBR = 7 V (typ.) and Rd = 1 (typ.) give: Vinput = 31.2 V Voutput = 7.95 V This confirms the very low remaining voltage across the device to be protected. It is also important to note that in this approximation the parasitic inductance effect was not taken into account. This could be few tenths of volts during few ns at the Vin side. This parasitic effect is not present at the Vout side due the low current involved after the resistance R. The measurements results shown below show very clearly (Figure 7.) the high efficiency of the ESD protection :

no influence of the parasitic inductances on Vout stage output clamping voltage very close to VBR (positive strike) and -VF (negative strike) Measurement board
Figure 6.
ESD SURGE 15 kV Air Discharge
TEST BOARD
UD1
Vin
Vout
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Application information Figure 7.
USBDFXXW5 Remaining voltage at both stages S1 (Vinput) and S2 (Voutput) during ESD surge
A. Positive surge
B. Negative surge
Note that the USBDFXXW5 is not only acting for positive ESD surges but also for negative ones. Negative disturbances are clamped close to ground voltage as shown in Figure 7.b.
2.3
Latch-up phenomena
The early ageing and destruction of IC's is often due to latch-up phenomena which is mainly induced by dV/dt. Thanks to its structure, the USBDFXXW5 provides a high immunity to latch-up phenomena by smoothing very fast edges.
2.4
Crosstalk behaviour
Figure 8. Crosstalk phenomena
RG1
Line 1
VG1 RG2 Line 2
RL1
1 VG1 + 1 2VG2
VG2
RL2
2 VG2 + 2 1VG1
DRIVERS
RECEIVERS
The crosstalk phenomena is due to the coupling between 2 lines. The coupling factor ( 12 or 21 ) increases when the gap across lines decreases, this is the reason why we provide crosstalk measurements for a monolithic device to guarantee negligeable crosstalk between the lines. In the example above, the expected signal on load RL2 is 2VG2, in fact the real voltage at this point has got an extra value 21VG1. This part of the VG1 signal represents the effect of the crosstalk phenomenon of the line 1 on the line 2. This phenomenon has to be taken into account when the drivers impose fast digital data or high frequency analog signals in the disturbing line. The perturbed line will be more affected if it works with low voltage signal or high load impedance (few k).
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USBDFXXW5
Application information
Figure 9.
Analog crosstalk measurements
Figure 10. Typical analog crosstalk results
Analog crosstalk (dB) 0 -20
50 TG OUT
TEST BOARD
RF IN
-40
50
UD1
Vg
-60 -80 -100 1 10 100 frequency (MHz) 1,000
Figure 8. gives the measurement circuit for the analog crosstalk application. In Figure 10., the curve shows the effect of the D+ cell on the D- cell. In usual frequency range of analog signals (up to 100 MHz) the effect on disturbed line is less than -46 dB. Figure 11. Digital crosstalk measurements configuration Figure 12. Digital crosstalk results
+5V 74HC04 Line 1 +5V VG1 Line 2
+5V 74HC04
Square Pulse Generator 5KHz
USBDF xxW5
b21 VG1
Figure 11. shows the measurement circuit used to quantify the crosstalk effect in a classical digital application. Figure 12. shows that in such a condition signal, from 0 to 5 V and rise time of few ns, the impact on the other line is less than 100 mV peak to peak (below the logic high voltage threshold). The measurements performed with falling edges give the same results.
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Application information
USBDFXXW5
2.5
Transition times
This low pass filter has been designed in order to meet the USB 1.1 standard requirements that implies the signal edges are maintained within the 4 ns-20 ns stipulated USB specification limits. Figure 13. Typical rise and fall times: measurements configuration
+5V +5V
74HC04 D+
+5V
74HC04
Square Pulse Generator
USBDF xxW5
D-
Figure 14. Typical rise and fall times
A. Rise time
B. Fall time
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USBDFXXW5
Package information
3
Package information
Table 3. SOT323-5L dimensions
Dimensions
A E
Ref.
Millimeters Min. Max. 1.1 0.1 1 0.3 0.18 2.2 1.35
Inches Min. 0.031 0 0.031 0.006 0.004 0.071 0.045 Max. 0.043 0.004 0.039 0.012 0.007 0.086 0.053
A
e b e D
0.8 0 0.8 0.15 0.1 1.8 1.15
A1 A2 b
A1 A2
c D E e
Q1
c L HE
0.65 Typ. 1.8 0.1 2.4 0.4
0.025 Typ. 0.071 0.004 0.094 0.016
H Q1
Figure 15. Recommended footprint (dimensions in mm)
0.3
1.0
2.9
1.0
0.35
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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Ordering information
USBDFXXW5
4
Ordering information
Type USBDF01W5 USBDF02W5 Order Code USBDF01W5 5.4 mg USBDF02W5 UD2 Weight Marking UD1 SOT323-5L 3000 Package Base Qty
5
Revision history
Date May-2000 7-Sep-2006 15-Sep-2006 Revision 1C 2 3 Initial release. Reformatted to current standard. Modified Operating junction temperature range in Table 1. . Corrected units of Rd to k instead of on page 1 Changes
10/11
USBDFXXW5
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